Understanding Verilog Blocking And Nonblocking Assignments
Understanding Verilog Blocking
and Non-blocking Assignments
International Cadence
User Group Conference
September 11, 1996
presented by
Stuart Sutherland
Sutherland HDL Consulting
About the Presenter
Stuart Sutherland has over 8 years of experience using Verilog with a variety of software tools. He
holds a BS degree in Computer Science, with an emphasis on Electronic Engineering, and has
worked as a design engineer in the defense industry, and as an Applications Engineer for Gateway
Design Automation (the originator of Verilog) and Cadence Design Systems. Mr. Sutherland has
been providing Verilog HDL consulting services since 1991. As a consultant, he has been actively
involved in using the Verilog langiage with a many different of software tools for the design of
ASICs and systems. He is a member of the IEEE 1364 standards committee and has been involved
in the specification and testing of Verilog simulation products from several EDA vendors, including
the Intergraph-VeriBest VeriBest simulator, the Mentor QuickHDL simulator, and the Frontline
CycleDrive cycle based simulator. In addition to Verilog design consutlting, Mr. Sutherland
provides expert on-site Verilog training on the Verilog HDL language and Programing Language
Interface. Mr. Sutherland is the author and publisher of the popular “Verilog IEEE 1364 Quick
Reference Guide” and the “Verilog IEEE 1364 PLI Quick Reference Guide”.
Please conact Mr. Sutherland with any questions about this material!
Sutherland HDL Consulting
Verilog Consulting and Training Services
phone: (503) 692-0898
22805 SW 92nd Place
fax: (503) 692-1512
Tualatin, OR 97062 USA
e-mail: stuart@sutherland.com
copyright notice
©1996
The material in this presentation is copyrighted by Sutherland HDL Consulting,
Tualatin, Oregon. The presentation is printed with permission as part of the
proceedings of the 1996 International Cadence User Group Conference. All rights
are reserved. No material from this presentation may be duplicated or transmitted by
any means or in any form without the express written permission of Sutherland HDL
Consulting.
Sutherland HDL Consulting
nd
22805 SW 92
Place
Tualatin, OR 97062 USA
phone: (503) 692-0898
fax: (503) 692-1512
e-mail: info@sutherland.com
4
Sutherland
Objectives
H D L
➤ The primary objective is to understand:
What type of hardware is represented
by blocking and non-blocking
assignments?
➤ The material presented is a subset of an advanced Verilog
HDL training course
5
Sutherland
Procedural Assignments
H D L
➤ Procedural assignment evaluation can be modeled as:
➤ Blocking
➤ Non-blocking
➤ Procedural assignment execution can be modeled as:
➤ Sequential
➤ Concurrent
➤ Procedural assignment timing controls can be modeled as:
➤ Delayed evaluations
➤ Delayed assignments
6
Blocking
Sutherland
Blocking
H D
Procedural Assignments
L
➤ The = token represents a blocking procedural assignment
➤ Evaluated and assigned in a single step
➤ Execution flow within the procedure is blocked until the
assignment is completed
➤ Evaluations of concurrent statements in the same time step
are blocked until the assignment is completed
These examples will not work Why not?
//sw
//sw a
a p b
p b y
ytte
e s in
s in w
w o
o rd
rd
//sw
//sw a
a p b
p b y
ytte
e s in
s in w
w o
o rd
rd
alway
alway s
s @(posedge clk)
@(posedge clk)
alway
alway s
s @(posedge clk)
@(posedge clk)
beg
begiin
n
fork
fork
word[15:8]
word[15:8] =
= word[ 7:0]
word[ 7:0];;
word[15:8]
word[15:8] =
= word[ 7:0]
word[ 7:0];;
word[ 7
word[ 7::0]
0] =
= word[15:8]
word[15:8];;
word[ 7
word[ 7::0]
0] =
= word[15:8]
word[15:8];;
end
end
jo
jo in
in
7
Non-Blocking
Sutherland
Non-Blocking
H D
Procedural Assignments
L
➤ The <= token represents a non-blocking assignment
➤ Evaluated and assigned in two steps:
x The right-hand side is evaluated immediately
y The assignment to the left-hand side is postponed until
other evaluations in the current time step are completed
➤ Execution flow within the procedure continues until a
timing control is encountered (flow is not blocked)
These examples will work Why?
//sw
//sw a
a p b
p b y
ytte
e s in
s in w
w o
o rd
rd
//sw
//sw a
a p b
p b y
ytte
e s in
s in w
w o
o rd
rd
alway
alway s
s @(posedge clk)
@(posedge clk)
alway
alway s
s @(posedge clk)
@(posedge clk)
begin
begin
fork
fork
word[15:8]
word[15:8] <=
<= word[ 7:0]
word[ 7:0];;
word[15:8]
word[15:8] <=
<= word[ 7:0]
word[ 7:0];;
word[ 7:0]
word[ 7:0] <=
<= word[15:8]
word[15:8];;
word[ 7:0]
word[ 7:0] <=
<= word[15:8]
word[15:8];;
end
end
join
join
8
Representing
Sutherland
Representing
H D
Simulation Time as Queues
L
➤ Each Verilog simulation time step is divided into 4 queues
Tim
Tim e
e 0
0 :
:
➤
➤ Q1 —
Q1 — (in any order)
(in any order) ::
➤ Evaluate RHS of all non-blocking assignments
➤ Evaluate RHS of all non-blocking assignments
➤ Evaluate RHS and change LHS of all blocking assignments
➤ Evaluate RHS and change LHS of all blocking assignments
➤ Evaluate RHS and change LHS of all continuous assignments
➤ Evaluate RHS and change LHS of all continuous assignments
➤ Evaluate inputs and change outputs of all primitives
➤ Evaluate inputs and change outputs of all primitives
➤ Evaluate and print output from $display and $write
➤ Evaluate and print output from $display and $write
➤
➤ Q2 —
Q2 — (in any order)
(in any order) ::
➤ Change LHS of all non-blocking assignments
➤ Change LHS of all non-blocking assignments
➤
➤ Q3 —
Q3 — (in any order)
(in any order) ::
➤ Evaluate and print output from $monitor and $strobe
➤ Evaluate and print output from $monitor and $strobe
➤ Call PLI with reason_synchronize
➤ Call PLI with reason_synchronize
➤
➤ Q4 :
Q4 :
➤ Call PLI with reason_rosynchronize
➤ Call PLI with reason_rosynchronize
Tim
Tim e
e 1
1 :
:
...
...
Note: this is an abstract view, not how simulation algorithms are implemented
9
Sequential
Sutherland
Sequential
H D
Procedural Assignments
L
➤ The order of evaluation is determinate
➤ A sequential blocking assignment evaluates and assigns
before continuing on in the procedure
always @(posedge clk)
begin
A = 1;
evaluate and assign A immediately
#5 B = A + 1;
delay 5 time units, then evaluate and assign
end
➤ A sequential non-blocking assignment evaluates, then
continues on to the next timing control before assigning
always @(posedge clk)
begin
A <= 1;
evaluate A immediately; assign at end of time step
#5 B <= A + 1;
delay 5 time units, then evaluate; then assign at
end
end of time step (clock + 5)
10
Concurrent
Sutherland
Concurrent
H D
Procedural Assignments
L
The order of concurrent evaluation is indeterminate
➤ Concurrent blocking assignments have unpredictable results
always @(posedge clk)
#5 A = A + 1;
Unpredictable Result:
(new value of B could be evaluated before
always @(posedge clk)
or after A changes)
#5 B = A + 1;
➤ Concurrent non-blocking assignments have predictable results
always @(posedge clk)
#5 A <= A + 1;
Predictable Result:
(new value of B will always be evaluated
always @(posedge clk)
before A changes)
#5 B <= A + 1;
11
Delayed Evaluation
Sutherland
Delayed Evaluation
H D
Procedural Assignments
L
➤ A timing control before an assignment statement will postpone
when the next assignment is evaluated
➤ Evaluation is delayed for the amount of time specified
begin
#5 A = 1;
delay for 5, then evaluate and assign
#5 A = A + 1;
delay 5 more, then evaluate and assign
B = A + 1;
no delay; evaluate and assign
end
What values do A and B contain after 10 time units?
12
Delayed Assignment
Sutherland
Delayed Assignment
H D
Procedural Assignments
L
➤ An intra-assignment delay places the timing control after the
assignment token
➤ The right-hand side is evaluated before the delay
➤ The left-hand side is assigned after the delay
always @(A)
A is evaluated at the time it changes, but
B = #5 A;
is not assigned to B until after 5 time units
always @(negedge clk)
D is evaluated at the negative edge of CLK,
Q <= @(posedge clk) D;
Q is changed on the positive edge of CLK
alway
alway s
s @(instru
@(instru ctor_input)
ctor_input)
if
if (m
(m orning)
orning)
understand = instructor_input;
understand = instructor_input;
else if
else if (af
(aftterno
erno on)
on)
understand = #5
understand = #5 instructor_in
instructor_in put;
put;
else if
else if (lun
(lun ch_tim
ch_tim e)
e)
understand = wait
understand = wait (!
(! lunch_tim
lunch_tim e)
e) instru
instru ctor_inp
ctor_inp ut;
ut;
13
Intra-Assignment Delays
Sutherland
Intra-Assignment Delays
H D
With Repeat Loops
L
➤ An edge-sensitive intra-assignment timing control permits a
special use of the repeat loop
➤ The edge sensitive time control may be repeated several
times before the delay is completed
➤ Either the blocking or the non-blocking assignment may be
used
alway
alway s
s @
@ (IN
(IN )
)
OUT <= re
OUT <= re pe
pe at (8) @
at (8) @ (
( posedge cl
posedge cl k)
k) IN;
IN;
The value of IN is evaluated when it changes, but is
not assigned to OUT until after 8 clock cycles
14
Choosing the
Sutherland
Choosing the
H D
Correct Procedural Assignment
L
➤ Which procedural assignment should be used to model a
combinatorial logic buffer?
always @(in)
always @(in)
#5 out = in;
out = #5 in;
always @(in)
always @(in)
#5 out <= in;
out <= #5 in;
➤ Which procedural assignment should be used to model a
sequential logic flip-flop?
always @(posedge clk)
always @(posedge clk)
#5 q = d;
q = #5 d;
always @(posedge clk)
always @(posedge clk)
#5 q <= d;
q <= #5 d;
➤ The following pages will answer these questions
15
Transition
Sutherland
Transition
H D
Propagation Methods
L
➤ Hardware has two primary propagation delay methods:
➤ Inertial delay models devices with finite switching speeds;
input glitches do not propagate to the output
10
20
30
40
50
60
10
20
30
40
50
60
Buffer with a 10 nanosecond propagation delay
➤ Transport delay models devices with near infinite
switching speeds; input glitches propagate to the output
10
20
30
40
50
60
10
20
30
40
50
60
Buffer with a 10 nanosecond propagation delay
16
Combinational Logic
Sutherland
Combinational Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
33 36
45
in
Blocking,
always @(in)
o1
zero delay
No delay
o1 = in;
Non-blocking,
always @(in)
o2
No delay
o2 <= in;
Blocking,
always @(in)
o3
inertial
Delayed evaluation
#5 o3 = in;
Non-blocking,
always @(in)
o4
Delayed evaluation
#5 o4 <= in;
Blocking,
always @(in)
o5
Delayed assignment
o5 = #5 in;
Non-blocking,
always @(in)
o6
transport
Delayed assignment
o6 <= #5 in;
17
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Sequential assignments
clk
➤ No delays
35
53
in
always @(posedge clk)
begin
y1
y1 = in;
y1
y2
y2 = y1;
y2
end
parall
paral el fl
lel flip
ip-flops
always @(posedge clk)
y1
begin
y1
y2
y1 <= in;
y2 <= y1;
y2
end
shift-register with zero delays
18
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Sequential assignments
clk
➤ Delayed evaluation
35
53
in
y1
always @(posedge clk)
begin
y2
y1
? ? ?
#5 y1 = in;
#5 y2 = y1;
y2
? ? ?
end
#5
#5
shift register with delayed clocks
y1
always @(posedge clk)
y2
begin
y1
? ? ?
#5 y1 <= in;
#5 y2 <= y1;
y2
#5
#5
? ? ?
end
shift register with delayed clocks
19
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Sequential assignments
clk
➤ Delayed assignment
35
53
in
y1
always @(posedge clk)
begin
y2
y1
y1 = #5 in;
#5
#5
y2 = #5 y1;
y2
end
#5
shift register delayed clock on second stage
y1
always @(posedge clk)
begin
y2
y1
y1 <= #5 in;
#5
#5
y2 <= #5 y1;
y2
end
shift register with delays
ys
20
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Concurrent assignments
clk
➤ No delays
35
53
in
y1
always @(posedge clk)
y1 = in;
y2
y1
?
always @(posedge clk)
y2
? ? ?
? ? ?
? ?
y2 = y1;
shift register
shift register with race conditi
th race condition
y1
always @(posedge clk)
y1 <= in;
y2
y1
always @(posedge clk)
y2
y2 <= y1;
shift-register with zero delays
21
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Concurrent assignments
clk
➤ Delayed evaluation
35
53
in
y1
always @(posedge clk)
#5 y1 = in;
y2
y1
? ? ?
?
always @(posedge clk)
y2
? ? ?
? ? ?
?
#5 y2 = y1;
#5
#5
shift register with race condition
y1
always @(posedge clk)
#5 y1 <= in;
y2
y1
? ? ?
always @(posedge clk)
y2
?
#5 y2 <= y1;
#5
shift register with race condition
22
Sequential Logic
Sutherland
Sequential Logic
H D
Procedural Assignments
L
➤ How will these procedural assignments behave?
10
20
30
40
50
60
➤ Concurrent assignments
clk
➤ Delayed assignment
35
53
in
y1
always @(posedge clk)
y1 = #5 in;
y2
y1
#5
#5
always @(posedge clk)
y2
y2 = #5 y1;
shift register, delay must be < clock period
y1
always @(posedge clk)
y1 <= #5 in;
y2
y1
#5
#5
always @(posedge clk)
y2
y2 <= #5 y1;
shift register with delays
23
Rules of Thumb for
Sutherland
Rules of Thumb for
H D
Procedural Assignments
L
➤ Combinational Logic:
➤ No delays: Use blocking assignments ( a = b; )
➤ Inertial delays: Use delayed evaluation blocking
assignments ( #5 a = b; )
➤ Transport delays: Use delayed assignment non-blocking
assignments ( a <= #5 b; )
➤ Sequential Logic:
➤ No delays: Use non-blocking assignments ( q <= d; )
➤ With delays: Use delayed assignment non-blocking
assignments ( q <= #5 d; )
24
An Exception to Non-blocking
Sutherland
An Exception to Non-blocking
H D
Assignments in Sequential Logic
L
➤ Do not use a non-blocking assignment if another statement in
the procedure requires the new value in the same time step
begin
#5 A <= 1;
What values do A
What values do A and B
and B contain
contain
#5 A <= A + 1;
after 10 ti
after 10 ti me
me units?
units? A is 2 B is 2
B <= A + 1;
end
always @(posedge clk)
Assume state
Assume state and next_
and next_ state
state
begin
are `STOP at the first clock,
case (state)
are `STOP at the first clock,
what is state:
`STOP: next_state <= `GO;
what is state:
- At the 2nd clock?
`STOP
`GO: next_state <= `STOP;
- At the 2nd clock?
endcase
-
- A
A t the 3rd
t the 3rd clock?
clock? `GO
state <= next_state;
-
- A
A t the 4th
t the 4th clock?
clock? `GO
end
-
- A
A t the 5th
t the 5th clock?
clock? `STOP
25
Exercise 3:
Sutherland
Exercise 3:
H D
Procedural Assignments
L
➤ Write a procedure for an adder (combinational logic) that
assigns C the sum of A plus B with a 7ns propagation delay.
always @
always @ (
( A or
A or B)
B)
#7
#7 C = A
C = A + B;
+ B;
➤ Write the procedure(s) for a 4-bit wide shift register (positive
edge triggered) of clock and has a 4ns propagation delay.
always @(
always @( po
po sed
sed g
g e
e clk)
clk)
always @(
always @( po
po sed
sed g
g e
e clk)
clk)
be
be gi
gi n
n
y1
y1 <= #4
<= #4 in
in;;
y
y 1
1 <= #4
<= #4 iin
n;;
always @(
always @( po
po sed
sed g
g e
e clk)
clk)
y
y 2
2 <= #4
<= #4 y1;
y1;
y2
y2 <= #4
<= #4 y
y 1
1;;
y
y 3
3 <= #4
<= #4 y2;
y2;
always @(
always @( po
po sed
sed g
g e
e clk)
clk)
ou
ou t <=
t <= #
# 4
4 y3
y3;;
y3
y3 <= #4
<= #4 y
y 2
2;;
end
end
always @(
always @( po
po sed
sed g
g e
e clk)
clk)
ou
ou t <=
t <= #4
#4 y3;
y3;
26
Exercise 3 (continued):
Sutherland
Exercise 3 (continued):
H D
Procedural Assignments
L
➤ Write a Verilog procedure for a “black box” ALU pipeline that
takes 8 clock cycles to execute an instruction. The pipeline
triggers on the positive edge of clock. The “black box” is
represented as call to a function named ALU with inputs A, B
and OPCODE.
How many Verilog
statements does it
take to model an
eight stage pipeline?
always @(
always @( po
po sed
sed g
g e
e clk
clk )
)
al
al u_out <
u_out < =
= re
re peat
peat (7) @
(7) @ (
( pos
pos e
e dge
dge cl
cl k) ALU(A,B,OPCODE);
k) ALU(A,B,OPCODE);
