Calibre Xrc
Parasitic Extraction
Calibre xRC
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Key Product Benefits:
• Seamless Invocation, Integration
and Cross-Probing. Calibre xRC is
easily invoked using Calibre
Interactive. Designers can cross-
probe results between layout,
schematic, source netlist, layout
netlist and LVS results. Results are
accessed by Calibre View and Calibre
RVE, both integrated into popular
Simulation setup
Plot waveforms
design frameworks.
Hierarchical netlisting capbilities.
When paired with a post layout hierar-
chical simulation tool, such as HSIM,
Calibre xRC provides a manageable
hierarchical netlist for large designs.
Full-Chip, Transistor-Level
Parasitic Extraction. Calibre xRC
capability is derived from the Calibre
hierarchical engine for excellent
Cross-probe
performance and accuracy on memo-
ry, analog, SoC and ASICdesigns.
Challenges of the Nanometer Era: Accurate Silicon
Modeling and Hierarchical Netlisting Capabilities
Tight Integration with Calibre
The nanometer era has revealed significant concerns:.physical effects are
LVS, the industry standard for
now the leading factor in the failure to achieve acceptable yield. However,
physical verification. By reading
current silicon-modeling techniques are unable to accurately predict if designs
LVS data structures directly, Calibre
xRC provides complete circuit netlist
will successfully manufacture. Traditional methods of black boxing, assump-
information integrated to the source
tive device measurement and gate-level extraction are not sufficient to meet
schematic for back-annotation.
the accuracy requirements of simulating sophisticated IC designs. This is a
task that can only be accomplished through exacting detail-actual device
• Mixed-Level Output for
measurement and transistor-level parasitic extraction-evaluated across the
Downstream Analysis. All transistor-
characteristics of the entire design.
and gate-level parasitic data (C, RC,
RCC) is stored and on-call in the
Calibre® xRC is a robust parasitic extraction tool that delivers accurate
Calibre xRC parasitic database to
parasitic data for comprehensive and accurate post-layout analysis and simula-
enable multiple analysis flows.
tion. Calibre xRC is able to extract interconnect parasitics hierarchically. The
result is a compact, hierarchical, transistor-level parasitic data, which can be
• One Rule File, One Flow. A single
back-annotated and simulated with full-chip circuit simulation tools, such as
parasitic extraction flow streamlines
HSIM. By using hierarchical storage and leveraging the circuit hierarchy and
the SoC design flow, reduces cycle
isomorphism during simulation, Calibre xRC and HSIM achieve breakthrough
time, eliminates multiple-tool
maintenance, and ensures a confident
performance for very large circuits, while delivering detailed SPICE-level
data transfer.
accuracy.
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Accuracy in Device Modeling:
Critical Link of Calibre LVS & Calibre xRC
In order to accurately model and analyze nanometer
designs, designers must be able to integrate parasitic infor-
mation into their design environment, and post-layout infor-
mation must be integrated as an entire circuit or subcircuit
suitable for simulation. This requires accurate extraction of
intentional devices, physically measured parameters and the
ability to properly back-annotate devices, gates, and nets
from the layout with the original design source.
To enable this, a tight integration between the LVS and
parasitic extraction tools is required. Proper back-annotation
Hierarchical DSPF back-annotation flow with
for simulation in any of the multiple transistor level flows
Calibre xRC and HSIM.
requires a connection to an LVS tool that enables multiple
parasitic extraction flows. The tools need to provide accurate
Calibre xRC and HSIM:
intentional device recognition for the variety of devices
Managing the Hierarchical, Transistor-
(transistor, inductor, capacitor, varactor, etc.) that will be
level Post-layout Analysis Flow
implemented in today's AMS designs.
As process sizes continue to shrink, integrated circuit
designers are forced to address an increasing number of
analysis issues that impact design closure, such as timing,
power, cross-talk noise and signal integrity. For some
types of designs, such as memories, these analysis
methods require the simulation of full-chip, transistor-
level parasitic effects. One of the biggest challenges
designers face is the vast amount of parasitic data gener-
ated in the process with the resulting bottleneck-the simu-
lation of these large netlists. A combination of high-
A copper process cross-section reveals complex
performance tools provides an efficient solution that
interactions of metal, poly, interconnect, diffusion and vias, all
potential.sources unintentional physical effects.Photo source: TSMC.
minimizes parasitic netlist size while delivering the neces-
sary extraction accuracy; coupled with fast, SPICE-level
In addition, Calibre xRC's new resistance and capacitance
engines, combined with Calibre LVS (layout vs. schematic)
accurate, hierarchical simulation performance. Designs
fully comprehend the boundary of the BSIM4.0 simulation
with a very.regular design structure and high hcell reuse,
model to accurately measure, extract and analyze these new
such as memories, will benefit the most from hierarchical
parasitics in a geometrically accurate way with smaller
parasitic extraction and analysis.
netlists, helping to preserve performance, capacity and yield.
Calibre xRC is able to extract interconnect parasitics
Tight integration among the design environment, LVS tool,
hierarchically. The result is a compact, hierarchical, tran-
parasitic extraction tool and analysis tool ensures efficient
sistor-level parasitic data, which can be back-annotated
data handling for both upstream design creation environ-
and simulated with full-chip circuit simulation tools, such
ments and downstream post-layout analysis. When a hierar-
as HSIM. By using hierarchical storage and leveraging
chical-based LVS tool is paired with a transistor-level para-
sitic extraction tool, it offers the designer the analysis
the circuit hierarchy and isomorphism during simulation,
capabilities required of an AMS SoC design: intentional
HSIM achieves breakthrough performance for very large
device recognition (with exact device parameters); parasitic
circuits, while delivering detailed SPICE-level accuracy.
device extraction at both transistor and gate levels; highest
accuracy for post-layout simulation; and backannotation of
simulation results to the source schematic.
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Calibre xRC for Seamless
Upstream Integration
Calibre is invoked from
• Transistor-Level Integration with
within the layout envi-
Calibre LVS. For parasitic netlists to
ronment via the Calibre
be useable in the designer’s simula-
Interactive graphic user
tion testbench, the extracted layout
interface.
netlist, including parasitic devices,
needs to be back-annotated to the
schematic netlist. A seamless inter-
face between LVS and extraction is
critical. When Calibre xRC is used
with Calibre LVS, it offers intentional
device recognition (with device
parameters) and parasitic device
extraction at both the transistor and
gate levels to provide the highest
Calibre’s results
accuracy for post-layout simulation
viewing environment
and to enable back-annotation of sim-
(RVE) displays
ulation results to the source schematic.
parasitic results
• Integrated with various design
with a tight link to
flows. Calibre xRC is fully integrated
Calibre LVS. From
with analog, memory and mixed sig-
the RVE menu, you
nal flows for today’s SoC designs.
can open the para-
• Integrated with Place and Route
sitic browsing
flows. Calibre xRC reads LEF/DEF
window,
and annotated GDS data produced by
shown below.
place and route tools, taking advan-
tage of the connectivity information
to produce gate-level netlists for gate-
level simulators. With the LVS/
extraction flow, Calibre xRC supports
DEF with GDS and gate-level extrac-
tion on full GDS data to provide tran-
sistor-level information or to enhance
the accuracy of gate-level results with
parasitic information from the cells.
• Calibre xRC with Calibre
Interactive. Calibre xRC is fully
integrated with Calibre Interactive,
giving users access to interactive
extraction from within popular layout
environments, such as Mentor
Graphics IC Station, Cadence®
Virtuoso and the Synposys® Milkway
and Galaxy environments.
• Parasitic Browsing with Calibre
RVE. Calibre RVE (results viewing
environment) enables viewing of
R, C, RCC results in the layout
environment.
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Calibre xRC Advanced
Simulation results of a full-
R and C Engines
chip design using Mentor
Calibre xRC's new resistance
Graphics Mach TA simulation
engine provides improved frac-
tool.
turing, including precise width and
resistor location for electro migration
analysis. It also offers enabling tech-
nologies for inductance extraction
and improved device pin handling,
improved gate pin placement and
user control over gate region extrac-
tion. Additionally, the algorithms are
Calibre View in the
hierarchical and much more effi-
Virtuoso environment,
cient. Better performance and
showing intentional devices
capacity is attained using the new
and extracted
paradigm while still providing
parameters at top of
improved accuracy.
screen, and parasitic
Calibre xRC's new capacitance
devices and their extracted
values at bottom of screen.
engine delivers a much tighter corre-
lation to field solver and silicon data,
greatly improving overall accuracy
Calibre xRC for Accurate
• On-the-Fly Reduction. The reduc-
of results. In addition, it has incor-
Downstream Analysis
tion supported in Calibre xRC
porated special models for vias,
includes Ticer (combination of AWE
Calibre xRC with Calibre View.
contacts and the poly-to-contact area,
and S-parameter techniques) and
Calibre extracted view provides an
as these are quite susceptible to
user-controlled thresholds and toler-
automated method for re-simulation
ances. Calibre xRC reduces parasitic
significant and elusive capacitance
directly from the design layout envi-
data, thereby reducing netlist size and
effects. Other solutions are taking
ronment. It is supported in the
improving simulation performance,
mathematical shortcuts to modeling
Calibre xRC flow, enabling graphical
while maintaining accuracy. (Visit
that will get them quick extraction
back-annotation and netlisting.
www.mentor.com/dsm to download
results, but will break down later in
• Parasitic Database Provides
the technical publication titled
Variety of Net Models. Calibre xRC
the design flow. Calibre xRC gives
TICER: Realizable Reduction of
parasitic database provides incremen-
Extracted RC Circuits.)
designers greater confidence in their
tal, hierarchical and multiple electric
post-layout simulation results, and
• Mixed-Level Extraction Enabled
views to enable analysis flows,
by a Parasitic Database. Calibre
therefore they do not have to build in
including noise, timing, power and
offers mixed-level data (transistor,
prohibitive design margins.
signal integrity.
gate and hierarchical) in the same
Calibre xL offers parasitic self-
• Hierarchical netlisting capabilities
parasitic extraction run with detail for
inductance extraction integrated with
with HSIM. Calibre xRC has the
R, C, RCC analysis.
Calibre xRC parasitic RC extraction
ability to output optimized hierarchi-
• Supports industry standard for-
cal parasitic data for signal and power
data, enabling accurate analysis of
mats including Spice, DSPF and
net analysis, integrating with Nassda's
high frequency effects in nanometer
SPEF outputs for running Mach TA,
post-layout hierarchical simulation
technology. (See the Calibre xL
Eldo, Advance MS, Calibre extracted
tool, HSIM.
view and Cadence® Spectre, as well
datasheet available at
as other standard tools.
www.mentor.com).
www.mentor.com
Calibre xRC: The Comprehensive Solution
for Nanometer Silicon Modeling at 90nm
While nanometer technology enables more and more func-
tionality on a single chip, it also brings a host of new phys-
ical effects that must be accounted for in simulation and
modeling. Finer line widths, longer interconnect, more
routing layers and burgeoning analog content are just the top
of the iceberg; lurking below are via capacitance, poly-
contact coupling, planarity fill, antenna effects, copper
processing issues, parasitic inductance and much more that
can produce functional flaws, which many times result in
failed silicon and costly respins. By implementing an
advanced nanometer silicon modeling flow that includes
Calibre xRC, designers can account for the complex device
and interconnect issues that so profoundly affect the accuracy
Calibre xRC solves nanometer design issues by cap-
of analysis and successful manufacture of a design.
turing complex silicon effects and accounting for
them in today’s design flows.
The Calibre Suite of Tools Offers a Complete Design-to-Silicon Platform
A powerful hierarchical polygon processing engine is at the
full-chip physical verification. The Calibre manufactura-
heart of the Calibre tool suite, which offers a complete
bility tool suite for Optical and Process Correction (OPC),
design to silicon solution. Each tool is an excellent point tool
Phase Shift Mask (PSM), Scatter Bars (SB) and Off-Axis
on its own, but the combination of Calibre DRC, Calibre
Illumination (OAI) deliver silicon accuracy, fastest turn-
LVS, Calibre xRC and Calibre RVE (results viewing envi-
around-time and excellent yield. Calibre MDP allows for
ronment) simplifies and strengthens the design flow.Calibre
seamless continuation of the data manipulations required for
Interactive provides a seamless, push-button interface,
mask data format conversion, keeping data hierarchically
enabling designers to use a single platform for cell/block and
represented as long as possible.
Visit our website at www.mentor.com
Copyright © 2006 Mentor Graphics Corporation. Mentor products and processes are registered trademarks of Mentor Graphics Corporation.
All other trademarks mentioned in this document are trademarks of their respective owners.
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