At89c51 8 Bit Microcontroller With 4 Kbytes Flash
AT89C51
Features
• Compatible with MCS-51™ Products
• 4 Kbytes of In-System Reprogrammable Flash Memory
Endurance: 1,000 Write/Erase Cycles
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
• Two 16-Bit Timer/Counters
8-Bit
• Six Interrupt Sources
• Programmable Serial Channel
Microcontroller
• Low Power Idle and Power Down Modes
with 4 Kbytes
Description
Flash
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4 Kbytes
of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufac-
tured using Atmel’s high density nonvolatile memory technology and is compatible with the
industry standard MCS-51™ instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory program-
mer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51
is a powerful microcomputer which provides a highly flexible and cost effective solution to
many embedded control applications.
The AT89C51 provides the following standard features: 4 Kbytes of Flash, 128 bytes of
RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a
full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is
(continued)
PDIP/Cerdip
Pin Configurations
P 1 . 0
1
4 0
V C C
P 1 . 1
2
3 9
P 0 . 0 ( A D 0 )
P 1 . 2
3
3 8
P 0 . 1 ( A D 1 )
P 1 . 3
4
3 7
P 0 . 2 ( A D 2 )
P 1 . 4
5
3 6
P 0 . 3 ( A D 3 )
P 1 . 5
6
3 5
P 0 . 4 ( A D 4 )
P 1 . 6
7
3 4
P 0 . 5 ( A D 5 )
P 1 . 7
8
3 3
P 0 . 6 ( A D 6 )
R S T
9
3 2
P 0 . 7 ( A D 7 )
( R X D ) P 3 . 0
1 0
3 1
E A / V P P
( T X D ) P 3 . 1
11
3 0
A L E / P R O G
( I N T 0 ) P 3 . 2
1 2
2 9
P S E N
( I N T 1 ) P 3 . 3
1 3
2 8
P 2 . 7 ( A 1 5 )
( T 0 ) P 3 . 4
1 4
2 7
P 2 . 6 ( A 1 4 )
( T 1 ) P 3 . 5
1 5
2 6
P 2 . 5 ( A 1 3 )
( W R ) P 3 . 6
1 6
2 5
P 2 . 4 ( A 1 2 )
( R D ) P 3 . 7
1 7
2 4
P 2 . 3 ( A 11 )
X TA L 2
1 8
2 3
P 2 . 2 ( A 1 0 )
X TA L 1
1 9
2 2
P 2 . 1 ( A 9 )
PQFP/TQFP
G N D
2 0
2 1
P 2 . 0 ( A 8 )
)
)
)
)
0
1
2
3
PLCC/LCC
I N D E X
(AD
(AD
(AD
(AD
)
)
)
)
C O R N E R
.4
.3
.2
.1
.0
.0
.1
.2
.3
0
1
2
3
P1
P1
P1
P1
P1
NC
VCC
P0
P0
P0
P0
(AD
(AD
(AD
(AD
I N D E X
C O R N E R
.4
.3
.2
.1
.0
.0
.1
.2
.3
4 4
4 2
4 0
3 8
3 6
3 4
4 3
4 1
3 9
3 7
3 5
P1
P1
P1
P1
P1
NC
VCC
P0
P0
P0
P0
P 1 . 5
1
3 3
P 0 . 4 ( A D 4 )
6
4
2
4 4
4 2
4 0
P 1 . 6
2
3 2
P 0 . 5 ( A D 5 )
5
3
1
P 1 . 5
4 3
4 1
7
3 9
P 0 . 4 ( A D 4 )
P 1 . 7
3
3 1
P 0 . 6 ( A D 6 )
P 1 . 6
8
3 8
P 0 . 5 ( A D 5 )
R S T
4
3 0
P 0 . 7 ( A D 7 )
P 1 . 7
9
3 7
P 0 . 6 ( A D 6 )
( R X D ) P 3 . 0
5
2 9
E A / V P P
R S T
1 0
3 6
P 0 . 7 ( A D 7 )
N C
6
2 8
N C
( R X D ) P 3 . 0
11
3 5
E A / V P P
( T X D ) P 3 . 1
7
2 7
A L E / P R O G
N C
1 2
3 4
N C
( I N T 0 ) P 3 . 2
8
2 6
P S E N
( T X D ) P 3 . 1
1 3
3 3
A L E / P R O G
( I N T 1 ) P 3 . 3
9
2 5
P 2 . 7 ( A 1 5 )
( I N T 0 ) P 3 . 2
1 4
3 2
P S E N
( T 0 ) P 3 . 4
1 0
2 4
P 2 . 6 ( A 1 4 )
( I N T 1 ) P 3 . 3
1 5
3 1
P 2 . 7 ( A 1 5 )
( T 1 ) P 3 . 5
11
2 3
P 2 . 5 ( A 1 3 )
( T 0 ) P 3 . 4
1 6
3 0
P 2 . 6 ( A 1 4 )
1 3
1 5
1 7
1 9
2 1
( T 1 ) P 3 . 5
1 7 19
2 1
2 3
2 9
P 2 . 5 ( A 1 3 )
2 5
2 7
1 2
1 4
1 6
1 8
2 0
2 2
1 8
2 0
2 2
2 4
2 6
2 8
1
2
2
1
.0
.1
.6
.
7
.0
.1
.
2
.
3
.
4
.6
.
7
.
2
.
3
.
4
3
NC
2
2
2
AL
3
AL
2
2
2
AL
AL
P2
P2
P3
P
GND
GND
P2
P2
P
P
P
P3
P
GND
P
P
P
)
)
)
XT
)
)
XT
)
)
)
XT
XT
1
R
1
R
10)
12)
10)
12)
(A8
(A9
(
RD)
(A8
(A9
(
RD)
(W
(W
0265E
(
A
(A1
(
A
(
A
(A1
(
A
3-33
Block Diagram
3-34
AT89C51
AT89C51
pullups and can be used as inputs. As inputs, Port 3 pins that are
Description (Continued)
externally being pulled low will source current (IIL) because of
designed with static logic for operation down to zero frequency
the pullups.
and supports two software selectable power saving modes. The
Port 3 also serves the functions of various special features of the
Idle Mode stops the CPU while allowing the RAM, timer/count-
AT89C51 as listed below:
ers, serial port and interrupt system to continue functioning. The
Power Down Mode saves the RAM contents but freezes the os-
Port Pin
Alternate Functions
cillator disabling all other chip functions until the next hardware
P3.0
RXD (serial input port)
reset.
P3.1
TXD (serial output port)
Pin Description
P3.2
INT0 (extenal interrupt 0)
P3.3
INT1 (extenal interrupt 1)
VCC
P3.4
T0 (timer 0 extenal input)
Supply voltage.
P3.5
T1 (timer 1 external input)
GND
P3.6
WR (extenal data memory write strobe)
Ground.
P3.7
RD (external data memory read strobe)
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output
Port 3 also receives some control signals for Flash programming
port each pin can sink eight TTL inputs. When 1s are written to
and programming verification.
port 0 pins, the pins can be used as high-impedance inputs.
RST
Port 0 may also be configured to be the multiplexed low-order
Reset input. A high on this pin for two machine cycles while the
address/data bus during accesses to external program and data
oscillator is running resets the device.
memory. In this mode P0 has internal pullups.
ALE/PROG
Port 0 also receives the code bytes during Flash programming,
Address Latch Enable output pulse for latching the low byte of
and outputs the code bytes during program verification. External
the address during accesses to external memory. This pin is also
pullups are required during program verification.
the program pulse input (PROG) during Flash programming.
Port 1
In normal operation ALE is emitted at a constant rate of 1/6 the
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The
oscillator frequency, and may be used for external timing or
Port 1 output buffers can sink/source four TTL inputs. When 1s
clocking purposes. Note, however, that one ALE pulse is
are written to Port 1 pins they are pulled high by the internal
skipped during each access to external Data Memory.
pullups and can be used as inputs. As inputs, Port 1 pins that are
If desired, ALE operation can be disabled by setting bit 0 of SFR
externally being pulled low will source current (IIL) because of
location 8EH. With the bit set, ALE is active only during a
the internal pullups.
MOVX or MOVC instruction. Otherwise, the pin is weakly
Port 1 also receives the low-order address bytes during Flash
pulled high. Setting the ALE-disable bit has no effect if the mi-
programming and program verification.
crocrontroller is in external execution mode.
Port 2
PSEN
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The
Program Store Enable is the read strobe to external program
Port 2 output buffers can sink/source four TTL inputs. When 1s
memory.
are written to Port 2 pins they are pulled high by the internal
When the AT89C51 is executing code from external program
pullups and can be used as inputs. As inputs, Port 2 pins that are
memory, PSEN is activated twice each machine cycle, except
externally being pulled low will source current (IIL) because of
that two PSEN activations are skipped during each access to ex-
the internal pullups.
ternal data memory.
Port 2 emits the high-order address byte during fetches from ex-
EA/VPP
ternal program memory and during accesses to external data
External Access Enable. EA must be strapped to GND in order
memory that use 16-bit addresses (MOVX @ DPTR). In this
to enable the device to fetch code from external program mem-
application it uses strong internal pullups when emitting 1s.
ory locations starting at 0000H up to FFFFH. Note, however,
During accesses to external data memory that use 8-bit ad-
that if lock bit 1 is programmed, EA will be internally latched on
dresses (MOVX @ RI), Port 2 emits the contents of the P2 Spe-
reset.
cial Function Register.
EA should be strapped to V
Port 2 also receives the high-order address bits and some control
CC for internal program executions.
signals during Flash programming and verification.
This pin also receives the 12-volt programming enable voltage
(V
Port 3
PP) during Flash programming, for parts that require 12-volt
VPP.
Port 3 is an 8-bit bidirectional I/O port with internal pullups. The
(continued)
Port 3 output buffers can sink/source four TTL inputs. When 1s
are written to Port 3 pins they are pulled high by the internal
3-35
Pin Description (Continued)
Power Down Mode
XTAL1
In the power down mode the oscillator is stopped, and the in-
Input to the inverting oscillator amplifier and input to the inter-
struction that invokes power down is the last instruction exe-
nal clock operating circuit.
cuted. The on-chip RAM and Special Function Registers retain
their values until the power down mode is terminated. The only
XTAL2
exit from power down is a hardware reset. Reset redefines the
Output from the inverting oscillator amplifier.
SFRs but does not change the on-chip RAM. The reset should
not be activated before VCC is restored to its normal operating
level and must be held active long enough to allow the oscillator
to restart and stabilize.
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier which can be configured for use as an on-
Figure 1. Oscillator Connections
chip oscillator, as shown in Figure 1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an ex-
C2
ternal clock source, XTAL2 should be left unconnected while
XTAL2
XTAL1 is driven as shown in Figure 2. There are no require-
ments on the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a divide-by-
C1
two flip-flop, but minimum and maximum voltage high and low
XTAL1
time specifications must be observed.
Idle Mode
In idle mode, the CPU puts itself to sleep while all the on-chip
GND
peripherals remain active. The mode is invoked by software.
The content of the on-chip RAM and all the special functions
registers remain unchanged during this mode. The idle mode can
be terminated by any enabled interrupt or by a hardware reset.
Notes: C1, C2 = 30 pF ± 10 pF for Crystals
It should be noted that when idle is terminated by a hardware
= 40 pF ± 10 pF for Ceramic Resonators
reset, the device normally resumes program execution, from
where it left off, up to two machine cycles before the internal
Figure 2. External Clock Drive Configuration
reset algorithm takes control. On-chip hardware inhibits access
to internal RAM in this event, but access to the port pins is not
inhibited. To eliminate the possibility of an unexpected write to
NC
XTAL2
a port pin when Idle is terminated by reset, the instruction fol-
lowing the one that invokes Idle should not be one that writes to
a port pin or to external memory.
EXTERNAL
OSCILLATOR
XTAL1
SIGNAL
GND
Status of External Pins During Idle and Power Down
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
3-36
AT89C51
AT89C51
Program Memory Lock Bits
On the chip are three lock bits which can be left unprogrammed
without a reset, the latch initializes to a random value, and holds
(U) or can be programmed (P) to obtain the additional features
that value until reset is activated. It is necessary that the latched
listed in the table below:
value of EA be in agreement with the current logic level at that
When lock bit 1 is programmed, the logic level at the EA pin is
pin in order for the device to function properly.
sampled and latched during reset. If the device is powered up
Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
U
U
U
No program lock features.
MOVC instructions executed from external program memory are disabled from
2
P
U
U
fetching code bytes from internal memory, EA is sampled and latched on reset, and
further programming of the Flash is disabled.
3
P
P
U
Same as mode 2, also verify is disabled.
4
P
P
P
Same as mode 3, also external execution is disabled.
Programming the Flash
The AT89C51 is normally shipped with the on-chip Flash mem-
4. Raise EA/VPP to 12 V for the high-voltage programming
ory array in the erased state (that is, contents = FFH) and ready
mode.
to be programmed. The programming interface accepts either a
5. Pulse ALE/PROG once to program a byte in the Flash
high-voltage (12-volt) or a low-voltage (VCC) program enable
array or the lock bits. The byte-write cycle is self-timed and
signal. The low voltage programming mode provides a conven-
typically takes no more than 1.5 ms. Repeat steps 1
ient way to program the AT89C51 inside the user’s system,
through 5, changing the address and data for the entire array
while the high-voltage programming mode is compatible with
or until the end of the object file is reached.
conventional third party Flash or EPROM programmers.
Data Polling: The AT89C51 features Data Polling to indicate
The AT89C51 is shipped with either the high-voltage or low-
the end of a write cycle. During a write cycle, an attempted read
voltage programming mode enabled. The respective top-side
of the last byte written will result in the complement of the writ-
marking and device signature codes are listed in the following
ten datum on PO.7. Once the write cycle has been completed,
table.
true data are valid on all outputs, and the next cycle may begin.
Data Polling may begin any time after a write cycle has been
VPP = 12 V
VPP = 5 V
initiated.
AT89C51
AT89C51
Ready/Busy: The progress of byte programming can also be
Top-Side Mark
xxxx
xxxx-5
monitored by the RDY/BSY output signal. P3.4 is pulled low
yyww
yyww
after ALE goes high during programming to indicate BUSY.
(030H)=1EH
(030H)=1EH
P3.4 is pulled high again when programming is done to indicate
READY.
Signature
(031H)=51H
(031H)=51H
(032H)=FFH
(032H)=05H
Program Verify: If lock bits LB1 and LB2 have not been pro-
grammed, the programmed code data can be read back via the
The AT89C51 code memory array is programmed byte-by-byte
address and data lines for verification. The lock bits cannot be
in either programming mode. To program any non-blank byte in
verified directly. Verification of the lock bits is achieved by ob-
the on-chip Flash Memory, the entire memory must be erased
serving that their features are enabled.
using the Chip Erase Mode.
Chip Erase: The entire Flash array is erased electrically by
Programming Algorithm: Before programming the AT89C51,
using the proper combination of control signals and by holding
the address, data and control signals should be set up according
ALE/PROG low for 10 ms. The code array is written with all
to the Flash programming mode table and Figures 3 and 4. To
"1"s. The chip erase operation must be executed before the code
program the AT89C51, take the following steps.
memory can be re-programmed.
1. Input the desired memory location on the address lines.
Reading the Signature Bytes: The signature bytes are read by
2. Input the appropriate data byte on the data lines.
the same procedure as a normal verification of locations 030H,
3. Activate the correct combination of control signals.
3-37
031H, and 032H, except that P3.6 and P3.7 must be pulled to a
Programming Interface
logic low. The values returned are as follows.
Every code byte in the Flash array can be written and the entire
(030H) = 1EH indicates manufactured by Atmel
array can be erased by using the appropriate combination of con-
(031H)
=
51H
indicates
89C51
trol signals. The write operation cycle is self-timed and once in-
(032H)
=
FFH
indicates
12
V
programming
itiated, will automatically time itself to completion.
(032H)
=
05H
indicates
5
V
programming
All major programming vendors offer worldwide support for the
Atmel microcontroller series. Please contact your local pro-
gramming vendor for the appropriate software revision.
Flash Programming Modes
ALE/
EA/
Mode
RST
PSEN
PROG
VPP
P2.6
P2.7
P3.6
P3.7
Write Code Data
H
L
H/12V(1)
L
H
H
H
Read Code Data
H
L
H
H
L
L
H
H
Write Lock
Bit - 1
H
L
H/12V
H
H
H
H
Bit - 2
H
L
(2)
H/12V
H
H
L
L
Bit - 3
H
L
H/12V
H
L
H
L
Chip Erase
H
L
H/12V
H
L
L
L
Read Signature Byte
H
L
H
H
L
L
L
L
Notes:
1. The signature byte at location 032H designates whether VPP
2. Chip Erase requires a 10 ms PROG pulse.
= 12 V or VPP = 5 V should be used to enable program-
ming.
3-38
AT89C51
AT89C51
Figure 3. Programming the Flash
Figure 4. Verifying the Flash
+5V
+5V
AT89C51
AT89C51
A0 - A7
A0 - A7
ADDR.
P1
VCC
ADDR.
P1
VCC
OOOOH/OFFFH
PGM
OOOOH/0FFFH
PGM DATA
P2.0 - P2.3
P0
P2.0 - P2.3
P0
(USE 10K
A8 - A11
DATA
A8 - A11
PULLUPS)
P2.6
P2.6
SEE FLASH
P2.7
ALE
PROG
SEE FLASH
P2.7
ALE
PROGRAMMING
PROGRAMMING
P3.6
P3.6
MODES TABLE
MODES TABLE
VIH
P3.7
P3.7
XTAL 2
EA
V
XTAL 2
EA
IH/VPP
4-24 MHz
4-24 MHz
XTAL 1
RST
V
XTAL 1
RST
V
IH
IH
GND
PSEN
GND
PSEN
Flash Programming and Verification Characteristics
TA = 21°C to 27°C, VCC = 5.0 ± 10%
Symbol
Parameter
Min
Max
Units
V
(1)
PP
Programming Enable Voltage
11.5
12.5
V
I
(1)
PP
Programming Enable Current
1.0
mA
1/tCLCL
Oscillator Frequency
4
24
MHz
tAVGL
Address Setup to PROG Low
48tCLCL
tGHAX
Address Hold After PROG
48tCLCL
tDVGL
Data Setup to PROG Low
48tCLCL
tGHDX
Data Hold After PROG
48tCLCL
tEHSH
P2.7 (ENABLE) High to VPP
48tCLCL
tSHGL
VPP Setup to PROG Low
10
µs
t
(1)
GHSL
VPP Hold After PROG
10
µs
tGLGH
PROG Width
1
110
µs
tAVQV
Address to Data Valid
48tCLCL
tELQV
ENABLE Low to Data Valid
48tCLCL
tEHQV
Data Float After ENABLE
0
48tCLCL
tGHBL
PROG High to BUSY Low
1.0
µs
tWC
Byte Write Cycle Time
2.0
ms
Note:
1. Only used in 12-volt programming mode.
3-39
Flash Programming and Verification Waveforms - High Voltage Mode
PROGRAMMING
VERIFICATION
P1.0 - P1.7
ADDRESS
ADDRESS
P2.0 - P2.3
tAVQV
PORT 0
DATA IN
DATA OUT
tDVGL
tGHDX
tAVGL
tGHAX
ALE/PROG
tSHGL
t
t
GHSL
GLGH
VPP
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
t
tEHQZ
ELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
READY
tWC
Flash Programming and Verification Waveforms - Low Voltage Mode
PROGRAMMING
VERIFICATION
P1.0 - P1.7
ADDRESS
ADDRESS
P2.0 - P2.3
tAVQV
PORT 0
DATA IN
DATA OUT
tDVGL
tGHDX
tAVGL
tGHAX
ALE/PROG
tSHGL
tGLGH
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
t
tEHQZ
ELQV
P2.7
(ENABLE)
tGHBL
P3.4
(RDY/BSY)
BUSY
READY
tWC
3-40
AT89C51
AT89C51
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under “Absolute Maximum
Operating Temperature................... -55°C to +125°C
Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
Storage Temperature...................... -65°C to +150°C
or any other conditions beyond those indicated in the operational
Voltage on Any Pin
sections of this specification is not implied. Exposure to absolute
with Respect to Ground ................... -1.0 V to +7.0 V
maximum rating conditions for extended periods may affect de-
vice reliability.
Maximum Operating Voltage ............................ 6.6 V
DC Output Current ....................................... 15.0 mA
D.C. Characteristics
TA = -40°C to 85°C, VCC = 5.0 V ± 20% (unless otherwise noted)
Symbol
Parameter
Condition
Min
Max
Units
VIL
Input Low Voltage
(Except EA)
-0.5
0.2 VCC-0.1
V
VIL1
Input Low Voltage (EA)
-0.5
0.2 VCC-0.3
V
VIH
Input High Voltage
(Except XTAL1, RST)
0.2 VCC+0.9
VCC+0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7 VCC
VCC+0.5
V
Output Low Voltage(1)
VOL
I
(Ports 1,2,3)
OL = 1.6 mA
0.45
V
Output Low Voltage(1)
VOL1
I
(Port 0, ALE, PSEN)
OL = 3.2 mA
0.45
V
IOH = -60 µA, VCC = 5 V ± 10%
2.4
V
Output High Voltage
VOH
(Ports 1,2,3, ALE, PSEN)
IOH = -25 µA
0.75 VCC
V
IOH = -10 µA
0.9 VCC
V
Output High Voltage
IOH = -800 µA, VCC = 5 V ± 10%
2.4
V
VOH1
(Port 0 in External Bus
IOH = -300 µA
0.75 VCC
V
Mode)
IOH = -80 µA
0.9 VCC
V
Logical 0 Input Current
IIL
V
(Ports 1,2,3)
IN = 0.45 V
-50
µA
Logical 1 to 0 Transition
ITL
V
Current (Ports 1,2,3)
IN = 2 V
-650
µA
Input Leakage Current
ILI
0.45 < V
(Port 0, EA)
IN < VCC
±10
µA
RRST
Reset Pulldown Resistor
50
300
KΩ
CIO
Pin Capacitance
Test Freq. = 1 MHz, TA = 25°C
10
pF
Active Mode, 12 MHz
20
mA
Power Supply Current
Idle Mode, 12 MHz
5
mA
ICC
Power Down Mode(2)
VCC = 6 V
100
µA
VCC = 3 V
40
µA
Notes: 1. Under steady state (non-transient) conditions, IOL must
If IOL exceeds the test condition, VOL may exceed the
be externally limited as follows:
related specification. Pins are not guaranteed to sink
Maximum IOL per port pin:10 mA
current
greater
than
the
listed
test
conditions.
Maximum IOL per 8-bit port:
2. Minimum VCC for Power Down is 2 V.
Port 0:26 mA
Ports 1,2, 3:15 mA
Maximum total IOL for all output pins:71 mA
3-41
A.C. Characteristics
(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all
other outputs = 80 pF)
External Program and Data Memory Characteristics
12 MHz Oscillator
16 to 24 MHz Oscillator
Symbol
Parameter
Units
Min
Max
Min
Max
1/tCLCL
Oscillator Frequency
0
24
MHz
tLHLL
ALE Pulse Width
127
2tCLCL-40
ns
tAVLL
Address Valid to ALE Low
28
tCLCL-13
ns
tLLAX
Address Hold After ALE Low
48
tCLCL-20
ns
tLLIV
ALE Low to Valid Instruction In
233
4tCLCL-65
ns
tLLPL
ALE Low to PSEN Low
43
tCLCL-13
ns
tPLPH
PSEN Pulse Width
205
3tCLCL-20
ns
tPLIV
PSEN Low to Valid Instruction In
145
3tCLCL-45
ns
tPXIX
Input Instruction Hold After PSEN
0
0
ns
tPXIZ
Input Instruction Float After PSEN
59
tCLCL-10
ns
tPXAV
PSEN to Address Valid
75
tCLCL-8
ns
tAVIV
Address to Valid Instruction In
312
5tCLCL-55
ns
tPLAZ
PSEN Low to Address Float
10
10
ns
tRLRH
RD Pulse Width
400
6tCLCL-100
ns
tWLWH
WR Pulse Width
400
6tCLCL-100
ns
tRLDV
RD Low to Valid Data In
252
5tCLCL-90
ns
tRHDX
Data Hold After RD
0
0
ns
tRHDZ
Data Float After RD
97
2tCLCL-28
ns
tLLDV
ALE Low to Valid Data In
517
8tCLCL-150
ns
tAVDV
Address to Valid Data In
585
9tCLCL-165
ns
tLLWL
ALE Low to RD or WR Low
200
300
3tCLCL-50
3tCLCL+50
ns
tAVWL
Address to RD or WR Low
203
4tCLCL-75
ns
tQVWX
Data Valid to WR Transition
23
tCLCL-20
ns
tQVWH
Data Valid to WR High
433
7tCLCL-120
ns
tWHQX
Data Hold After WR
33
tCLCL-20
ns
tRLAZ
RD Low to Address Float
0
0
ns
tWHLH
RD or WR High to ALE High
43
123
tCLCL-20
tCLCL+25
ns
3-42
AT89C51
AT89C51
External Program Memory Read Cycle
tLHLL
ALE
tPLPH
tAVLL
tLLIV
tLLPL
tPLIV
PSEN
t
t
PXAV
PLAZ
t
t
PXIZ
LLAX
tPXIX
PORT 0
A0 - A7
INSTR IN
A0 - A7
tAVIV
PORT 2
A8 - A15
A8 - A15
External Data Memory Read Cycle
tLHLL
ALE
tWHLH
PSEN
tLLDV
tRLRH
tLLWL
RD
tLLAX
t
t
RLDV
tRHDZ
AVLL
tRLAZ
tRHDX
PORT 0
A0 - A7 FROM RI OR DPL
DATA IN
A0 - A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
3-43
External Data Memory Cycle
tLHLL
ALE
tWHLH
PSEN
tLLWL
tWLWH
WR
tLLAX
t
t
t
AVLL
QVWX
WHQX
tQVWH
PORT 0
A0 - A7 FROM RI OR DPL
DATA OUT
A0 - A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH
A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
tCHCX
t
t
CLCH
CHCL
V
- 0.5 V
CC
0.7 VCC
0.2 V
- 0.1 V
CC
0.45 V
tCLCX
tCLCL
External Clock Drive
Symbol
Parameter
Min
Max
Units
1/tCLCL
Oscillator Frequency
0
24
MHz
tCLCL
Clock Period
41.6
ns
tCHCX
High Time
15
ns
tCLCX
Low Time
15
ns
tCLCH
Rise Time
20
ns
tCHCL
Fall Time
20
ns
3-44
AT89C51
AT89C51
Serial Port Timing: Shift Register Mode Test Conditions
(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)
12 MHz Osc
Variable Oscillator
Symbol
Parameter
Min
Max
Min
Max
Units
tXLXL
Serial Port Clock Cycle Time
1.0
12tCLCL
µs
tQVXH
Output Data Setup to Clock Rising Edge
700
10tCLCL-133
ns
tXHQX
Output Data Hold After Clock Rising Edge
50
2tCLCL-33
ns
tXHDX
Input Data Hold After Clock Rising Edge
0
0
ns
tXHDV
Clock Rising Edge to Input Data Valid
700
10tCLCL-133
ns
Shift Register Mode Timing Waveforms
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tQVXH
tXHQX
WRITE TO SBUF
0
1
2
3
4
5
6
7
t
OUTPUT DATA
t
XHDX
SET TI
XHDV
CLEAR RI
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
INPUT DATA
SET RI
AC Testing Input/Output Waveforms (1)
Float Waveforms (1)
V
- 0.5 V
CC
+0.1 V
-0.1 V
0.2 V
+ 0.9 V
V
V
CC
LOAD
OL
TEST POINTS
V
Timing Reference
LOAD
Points
0.2 V
- 0.1 V
-0.1 V
CC
V
V
+0.1 V
0.45 V
LOAD
OL
Note:
1. AC Inputs during testing are driven at VCC - 0.5 V for a
Note:
1. For timing purposes, a port pin is no longer floating when a
logic 1 and 0.45 V for a logic 0. Timing measurements
100 mV change from load voltage occurs. A port pin be-
are made at VIH min. for a logic 1 and VIL max. for a
gins to float when a 100 mV change from the loaded
logic 0.
VOH/VOL level occurs.
3-45
Ordering Information
Speed
Power
Ordering Code
Package
Operation Range
(MHz)
Supply
12
5 V ± 20%
AT89C51-12AC
44A
Commercial
AT89C51-12JC
44J
(0°C to 70°C)
AT89C51-12PC
40P6
AT89C51-12QC
44Q
AT89C51-12AI
44A
Industrial
AT89C51-12JI
44J
(-40°C to 85°C)
AT89C51-12PI
40P6
AT89C51-12QI
44Q
AT89C51-12AA
44A
Automotive
AT89C51-12JA
44J
(-40°C to 125°C)
AT89C51-12PA
40P6
AT89C51-12QA
44Q
5 V ± 10%
AT89C51-12DM
40D6
Military
AT89C51-12LM
44L
(-55°C to 125°C)
AT89C51-12DM/883
40D6
Military/883C
AT89C51-12LM/883
44L
Class B, Fully Compliant
(-55°C to 125°C)
16
5 V ± 20%
AT89C51-16AC
44A
Commercial
AT89C51-16JC
44J
(0°C to 70°C)
AT89C51-16PC
40P6
AT89C51-16QC
44Q
AT89C51-16AI
44A
Industrial
AT89C51-16JI
44J
(-40°C to 85°C)
AT89C51-16PI
40P6
AT89C51-16QI
44Q
AT89C51-16AA
44A
Automotive
AT89C51-16JA
44J
(-40°C to 125°C)
AT89C51-16PA
40P6
AT89C51-16QA
44Q
20
5 V ± 20%
AT89C51-20AC
44A
Commercial
AT89C51-20JC
44J
(0°C to 70°C)
AT89C51-20PC
40P6
AT89C51-20QC
44Q
AT89C51-20AI
44A
Industrial
AT89C51-20JI
44J
(-40°C to 85°C)
AT89C51-20PI
40P6
AT89C51-20QI
44Q
24
5 V ± 20%
AT89C51-24AC
44A
Commercial
AT89C51-24JC
44J
(0°C to 70°C)
AT89C51-24PC
44P6
AT89C51-24QC
44Q
AT89C51-24AI
44A
Industrial
AT89C51-24JI
44J
(-40°C to 85°C)
AT89C51-24PI
44P6
AT89C51-24QI
44Q
3-46
AT89C51
AT89C51
Ordering Information
Package Type
44A
44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
40D6
40 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip)
44J
44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
44L
44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)
40P6
40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44Q
44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)
3-47
Document Outline
