Application Note 140 Cmos Schmitt Trigger A Uniquely Versatile ...
CMOS
CMOS Schmitt Trigger—A
Fairchild Semiconductor
Application Note 140
Uniquely Versatile Design
June 1975
Schmitt
Component
INTRODUCTION
N-channel. Transistors P3 and N3 are operating in the
The Schmitt trigger has found many applications in numer-
source follower mode and introduce hysteresis by feeding
ous circuits, both analog and digital. The versatility of a TTL
back the output voltage, out', to two different points in the
T
rigger
Schmitt is hampered by its narrow supply range, limited in-
stack.
terface capability, low input impedance and unbalanced out-
When the input is at 0V, transistors P1 and P2 are ON, and
put characteristics. The Schmitt trigger could be built from
N1, N2 and P3 are OFF. Since out' is high, N3 is ON and act-
discrete devices to satisfy a particular parameter, but this is
ing as a source follower, the drain of N1, which is the source
a careful and sometimes time-consuming design.
of N2, is at V
− V
. If the input voltage is ramped up to
—
CC
TH
The CMOS Schmitt trigger, which comes six to a package,
one threshold above ground transistor N1 begins to turn ON,
A
uses CMOS characteristics to optimize design and advance
N1 and N3 both being ON form a voltage divider network bi-
Uniquely
into areas where TTL could not go. These areas include: in-
asing the source of N2 at roughly half the supply. When the
terfacing with op amps and transmission lines, which oper-
input is a threshold above 1⁄2 V
, N2 begins to turn ON and
CC
ate from large split supplies, logic level conversion, linear op-
regenerative switching is about to take over. Any more volt-
eration,
and
special
designs
relying
on
a
CMOS
age on the input causes out' to drop. When out' drops, the
characteristic. The CMOS Schmitt trigger has the following
source of N3 follows its gate, which is out', the influence of
advantages:
N3 in the voltage divider with N1 rapidly diminishes, bringing
out' down further yet. Meanwhile P3 has started to turn ON,
•
High impedance input (1012Ω typical)
V
its gate being brought low by the rapidly dropping out'. P3
•
Balanced input and output characteristics
ersatile
turning ON brings the source of P2 low and turns P2 OFF.
— Thresholds are typically symmetrical to 1⁄2 VCC
With P2 OFF, out' crashes down. The snapping action is due
— Outputs source and sink equal currents
to greater than unity loop gain through the stack caused by
positive feedback through the source follower transistors.
— Outputs drive to supply rails
When the input is brought low again an identical process oc-
•
Positive and negative-going thresholds show low varia-
curs in the upper portion of the stack and the snapping action
Design
tion with respect to temperature
takes place when the lower threshold its reached.
•
Wide supply range (3V–15V), split supplies possible
Out' is fed into the inverter formed by P4 and N4; another in-
•
Low power consumption, even during transitions
verter built with very small devices, P5 and N5, forms a latch
•
High noise immunity, 0.70 V
typical
which stabilizes out'. The output is an inverting buffer ca-
CC
Applications demonstrating how each of these character-
pable of sinking 360 µA or two LPTTL loads.
Component
istics can become a design advantage will be given later
The typical transfer characteristics are shown in Figure 2;
in the application note.
the guaranteed trip point range is shown in Figure 3.
ANALYZING THE CMOS SCHMITT
The input of the Schmitt trigger goes through a standard in-
put protection and is tied to the gates of four stacked de-
vices. The upper two are P-channel and the lower two are
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© 1998 Fairchild Semiconductor Corporation
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FIGURE 1. CMOS Schmitt Trigger
WHAT HYSTERESIS CAN DO FOR YOU
Hysteresis is the difference in response due to the direction
of input change. A noisy signal that traverses the threshold of
a comparator can cause multiple transitions at the output, if
the response time of the comparator is less than the time be-
tween spurious effects. A Schmitt trigger has two thresholds:
any spurious effects must be greater than the threshold dif-
ference to cause multiple transitions. With a CMOS Schmitt
at V
= 10V there is typically 3.6V of threshold difference,
CC
enough hysteresis to overcome almost any spurious signal
on the input.
A comparator is often used to recover information sent down
an unbalanced transmission line. The threshold of the com-
parator is placed at one half the signal amplitude (See Figure
4b). This is done to prevent slicing level distortion. If a 4 µs
wide signal is sent down a transmission line a 4 µs wide sig-
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nal should be received or signal distortion occurs. If the com-
FIGURE 2. Typical CMOS Transfer Characteristics for
parator has a threshold above half the signal amplitude, then
Three Different Supply Voltages
positive pulses sent are shorter and negative pulses are
lengthened (See Figure 4c). This is called slicing level distor-
tion. The Schmitt trigger does have a positive offset, V
, but
T+
it also has a negative offset V
. In CMOS these offsets are
T−
approximately symmetrical to half the signal level so a 4 µs
wide pulse sent is also recovered (see Figure 4d). The re-
covered pulse is delayed in time but the length is not
changed, so noise immunity is achieved and signal distortion
is not introduced because of threshold offsets.
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FIGURE 3. Guaranteed Trip Point Range
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2
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FIGURE 4. CMOS Schmitt Trigger Ignores Noise
3
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a) Capacitor impedance at lowest operating frequency should be much less than R | R = 1⁄2R.
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b) By using split supply (±1.5V to ±7.5V) direct interface is achieved.
FIGURE 5. Sine to Square Wave Converter with Symmetrical Level Detection
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Where R1C1 ≅ 1/fMAX and R2C2 ≅ response time of voltmeter
VOUT = fR2C1∆ where ∆V = VCC
FIGURE 6. Diode Dump Tach Accepts any Input Waveform
APPLICATIONS OF THE CMOS SCHMITT
dumped to ground through D1. On negative output swings,
Most of the following applications use a CMOS Schmitt char-
current is pulled from the inverting op amp node through D2
acteristic to either simplify design or increase performance.
and transformed into an average voltage by R2 and C2.
Some of the applications could not be done at all with an-
Since the CMOS Schmitt pulls completely to the supply rails
other logic family.
the voltage change across the capacitor is just the supply
The circuit in Figure 5a is the familiar sine to square wave
voltage.
converter. Because of input symmetry the Schmitt trigger is
Schmitt triggers are often used to generate fast transitions
easily biased to achieve a 50% duty cycle. The high input im-
when a slowly varying function exceeds a predetermined
pedance simplifies the selection of the biasing resistors and
level. In Figure 7, we see a typical circuit, a light activated
coupling capacitor. Since CMOS has a wide supply range
switch. The high impedance input of the CMOS Schmitt trig-
the Schmitt trigger could be powered from split supplies (see
ger makes biasing very easy. Most photo cells are several
Figure 5b). This biases the mean threshold value around
kΩ brightly illuminated and a couple MΩ dark. Since CMOS
zero and makes direct coupling from an op amp output pos-
has a 1012 typical input impedance, no effects are felt on the
sible.
input when the output changes. The selection of the biasing
In Figure 4, we see a frequency to voltage converter that ac-
resistor is just the solution of a voltage divider equation.
cepts many waveforms with no change in output voltage. Al-
A CMOS application note wouldn’t be complete without a low
though the energy in the waveforms are quite different, it is
power application. Figure 8 shows a simple RC oscillator.
only the frequency that determines the output voltage. Since
With only six R’s and C’s and one Hex CMOS trigger, six low
the output of the CMOS Schmitt pulls completely to the sup-
power oscillators can be built. The square wave output is ap-
ply rails, a constant voltage swing across capacitor C1
proximately 50% duty cycle because of the balanced input
causes a current to flow through the capacitor, dependent
and output characteristics of CMOS. The output frequency
only on frequency. On positive output swings, the current is
equation assumes that t = t ≥ t
+ t
.
1
2
pd0
pd1
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FIGURE 7. Light activated switch couldn’t be simpler. The input voltage rises as light intensity increases, when VT+
is reached, the output will go low and remain low until the intensity is reduced significantly.
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FIGURE 8. Simplest RC Oscillator? Six R’s and C’s make the CMOS Schmitt into six low power oscillators. Balanced
input and output characteristics give the output frequency a typically 50% Duty Cycle.
5
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A B + AB = Error
Error is detected when transmission line is unbalanced in either direction.
a) Differential Error Detector
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Transmitted data appears at F as long as transmission line is balanced,
unbalanced data is ignored and error is detected by above circuit.
b) Differential Line Receiver
Truth Table
A
B
F
0
0
NC
0
1
0
1
0
1
1
1
NC
NC = No Change
1/3 MM74C14 Schmitt Trigger
1/6 MM74C04 Inverter
3/4 MM74C00 2-Input NAND
1/3 MM74C10 3-Input NAND
FIGURE 9. Increase noise immunity by using the CMOS Schmitt trigger to demodulate a balanced transmission line.
We earlier saw how the CMOS Schmitt increased noise im-
breakdown. The input voltage can go positive until reverse
munity on an unbalanced transmission line. Figure 9 shows
biased D2 breaks down through forward bias D3, which is
an application for a balanced or differential transmission line.
35V above ground. The input voltage can go negative until
The circuit in Figure 7 a is CMOS EXCLUSIVE OR, the
reverse biased D1 breaks down through forward bias D2,
MM74C86, which could also be built from inverters, and
which is 35V below V
. Adequate input protection against
CC
NAND gates. If unbalanced information is generated on the
static charge is still maintained.
line by signal crosstalk or external noise sources, it is recog-
CMOS can be linear over a wide voltage range if proper con-
nized as an error.
sideration is paid to the biasing of the inputs. Figure 11
The circuit in Figure 9b is a differential line receiver that re-
shows a simple VCO made with a CMOS inverter, acting as
covers balanced transmitted data but ignores unbalanced
an integrator, and a CMOS Schmitt, acting as a comparator
signals by latching up. If both circuits of Figure 9 were used
with hysteresis. The inverter integrates the positive differ-
together, the error detector could signal the transmitter to
ence between its threshold and the input voltage V
. The in-
IN
stop transmission and the line receiver would remember the
verter output ramps up until the positive threshold of the
last valid information bit when unbalanced signals persisted
Schmitt trigger is reached. At that time, the Schmitt trigger
on the line. When balanced signals are restored, the receiver
output goes low, turning on the transistor through R
and
S
can pick up where it left off.
speeding up capacitor C . Hysteresis keeps the output low
S
The standard voltage range for CMOS inputs is V
+ 0.3V
until the integrating capacitor C is discharged through R .
CC
D
and ground − 0.3V. This is because the input protection net-
Resistor R
should be kept much smaller than RC to keep
D
work is diode clamped to the supply rails. Any input exceed-
reset time negligible. The output frequency is given by
ing the supply rails either sources or sinks a large amount of
current through these diodes. Many times an input voltage
range exceeding this is desirable; for example, transmission
lines often operate from ±12V and op amps from ±15V. A
The frequency dependence with control voltage is given by
solution to this problem is found in the MM74C914. This new
the derivative with respect to Vin. So,
device has an uncommon input protection that allows the in-
put signal to go to 25V above ground, and 25V below V
.
CC
This means that the Schmitt trigger in the sine to square
wave converter, in Figure 6b, could be powered by ±1.5V
supplies and still be directly compatible with an op amp pow-
where the minus sign indicates that the output frequency in-
ered by ±15V supplies.
creases as the input is brought further below the inverter
A standard input protection circuit and the new input protec-
threshold. The maximum output frequency occurs when VIN
tion are shown in Figure 10. The diodes shown have a 35V
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6
is at ground and the frequency will decrease as V
is raised
IN
up and will finally stop oscillating at the inverter threshold,
approximately 0.55 V
.
CC
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a)
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b)
FIGURE 10. Input protection diodes, in a) Normally limit the input voltage swing to 0.3V above V
and 0.3V below
CC
ground. In b) D2 or D1 is reverse biased allowing input swings of 25V above ground or 25V below V
.
CC
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0≤VIN≤1⁄2 VCC
FIGURE 11. Linear CMOS (Voltage Controller Oscillator)
The pulses from the VCO output are quite narrow because
sistor must charge it from its supply. When the input voltage
the reset time is much smaller than the integration time.
of the Schmitt reaches V
, the Schmitt output will go low
T+
Pulse stretching comes quite naturally to a Schmitt trigger. A
sometime after the input pulse has gone low.
one-shot or pulse stretcher made with an inverter and
Schmitt trigger is shown in Figure 12. A positive pulse com-
THE SCHMITT SOLUTION
ing into the inverter causes its output to go low, discharging
The Schmitt trigger, built from discrete parts, is a careful and
the capacitor through the diode D1. The capacitor is rapidly
sometimes time-consuming design. When introduced in inte-
discharged, so the Schmitt input is brought low and the out-
grated TTL, a few years ago, many circuit designers had re-
put goes positive. Check the size of the capacitor to make
newed interest because it was a building block part. The in-
sure that inverter can fully discharge the capacitor in the in-
put characteristics of TTL often make biasing of the trigger
put pulse time, or
input difficult. The outputs don’t source as much as they sink,
so multivibrators don’t have 50% duty cycle, and a limited
supply range hampers interfacing with non-5V parts.
The CMOS Schmitt has a very high input impedance with
thresholds approximately symmetrical to one half the supply.
where ∆V = V
for CMOS, and ∆T is the input pulse width.
CC
A high voltage input is available. The outputs sink and
For very narrow pulses, under 100 ns, the capacitor can be
source equal currents and pull directly to the supply rails.
omitted and a large resistor will charge up the CMOS gate
A wide threshold range, wide supply range, high noise immu-
capacitance just like a capacitor.
nity, low power consumption, and low board space make the
When the inverter input returns to zero, the blocking diode
CMOS Schmitt a uniquely versatile part.
prevents the inverter from charging the capacitor and the re-
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Use the Schmitt trigger for signal conditioning, restoration of
The CMOS Schmitt is one step closer to making design lim-
levels, discriminating noisy signals, level detecting with hys-
ited only by the imagination of the designer.
teresis, level conversion between logic families, and many
other useful functions.
Component
Design
ersatile
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V
TO = tIN + T
FIGURE 12. Pulse Stretcher. A CMOS inverter discharges a capacitor, a blocking diode allows charging through R
only. Schmitt trigger output goes low after the RC delay.
Uniquely
A
—
rigger
T
Schmitt
CMOS
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AN-140
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